Technical Field
The present disclosure relates to alignment structures formed on a plurality of wafers configured to be aligned to form a multichip stack in a single package.
Description of the Related Art
As consumer demand increases for smaller multifunction devices, manufacturers face significant challenges to integrate different semiconductor technologies on a single die. Multichip packages have become increasingly popular to increase device density and to combine traditionally incompatible technologies, such as logic, memory, and micro-electromechanical systems (MEMS). For example, as cell phones morph into personal entertainment systems, manufacturers look for ways to integrate multiple technologies, like SRAM, DRAM, flash, logic, analog, and radio frequency, into one relatively thin package.
Multichip packages also address some of the limitations that have arisen with respect to two-dimensional scaling. The multichip packages may be aligned and bonded at the wafer level or as individual die. Each of the die to be included in a multichip package may be formed on a single wafer dedicated to a particular technology. For example, one die may be manufactured to be a processor that is configured to be packaged with a MEMS sensor, which is separately manufactured on another wafer.
These vertically stacked chips formed from multiple die offer improved density and performance. The challenges to integrate traditionally incompatible processes on a single wafer are avoided by forming incompatible technologies on individual wafers and packaging them in the single package.
FIG. 1 is a vertical stack 10 of six wafers 12a-12f aligned and bonded according to a known method of alignment. Each wafer 12a-12f is formed independently from the other wafers to have a plurality of through silicon vias (TSVs) 14 in similar locations. After the processing to form a plurality of die on the wafers 12a-12f is complete, the wafers 12a-12f are thinned to approximately 70 microns. The thinning reduces the size and weight of the final vertically stacked multi-chip package.
The TSVs 14 can be used for alignment and to form electrical communications between wafers. The TSVs 14 may be formed by deep reactive ion etching before or after the wafers 12a-12f are thinned. Typically, the TSVs are formed after the devices are formed on the wafers. The TSVs 14 in FIG. 1 are annular metal TSVs that are shown in cross-section as two vertical pillars 16 through each wafer 12a-12f. A top pad 18 and a bottom pad 20 are formed on a top and bottom surface of each wafer 12a-12f after the wafer is thinned. The top and bottom pads 18 and 20 are solder interconnects that electrically connect the TSVs 14 of the wafers 12a-12f. 
The wafers 12a-12f in FIG. 1 are not accurately aligned. For example, the annular TSVs 14 are all formed to have the same diameter. In the cross-section of FIG. 1, a width between each pillar 16 of each TSV 14 varies from wafer to wafer. More particularly, the width between the pillars 16 of the TSVs 14 of wafer 12a is smaller than the width between the pillars 16 of wafer 12b. This variation in width indicates that the TSVs 14 of each wafer 12a-12f are not aligned.
Alignment is achieved when the top pads 18 are in contact with respective bottom pads 20 of an adjacent wafer. The inaccuracy of this method of alignment is also shown by considering a central axis 22 of each annular TSV 14. If the wafers 12a-12f were accurately aligned, the central axis 22 of each annular TSV 14 would align. Clearly, the central axes 22 of the TSVs 14 are shifted with respect to each other. This imprecise alignment affects electrical communication between the chips and impacts the reliability of device performance.